Fast voltage level shifter circuit

ABSTRACT

A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. patent application Ser. No. 14/953,053, filed Nov. 27, 2015, which is a continuation of U.S. patent application Ser. No. 14/279,830, filed May 16, 2014, which is a continuation of U.S. patent application Ser. No. 13/015,064, filed Jan. 27, 2011, which claims priority to U.S. provisional application No. 61/298,555 filed on Jan. 27, 2010 by the present inventor, each of which is incorporated by reference herein as to their entireties.

BACKGROUND

1. Technical Field

The present invention relates to voltage level switching and, more particularly to a voltage level shifter circuit and a method for the operation of the voltage level shifter circuit.

2. Description of Related Art

Reference is now made to FIG. 1 which shows a current mirror circuit 10 according to conventional art. The base of a transistor Q₁ is connected to the base of a transistor Q₂, along with both of the emitters of Q₁ and Q₂ typically connected to ground or another common voltage point. A link connects the collector of Q₁ to the bases of Q₁ and Q₂. The collector of Q₁ also connects to voltage supply (V_(cc)) via a resistor R. The voltage output (V_(out)) of current mirror circuit 10 is between the collector of Q₂ and ground or between the collector of Q₂ and another voltage point.

Bipolar transistors such as Q₁ or Q₂ have a current gain (β) which is the ratio of the collector current to the base current. The relationship between I_(REF) and I_(OUT) is given by equation Eq. 1 below:

$\begin{matrix} {I_{OUT} = {\left( \frac{\beta}{\beta + 2} \right)I_{REF}}} & {{Eq}.\; 1} \end{matrix}$

Where the current gain (β) is high I_(REF) equals I_(OUT) and I_(REF) is said to ‘mirror’ I_(OUT). The current being ‘mirrored’ can be, and sometimes is, a varying signal current. The current mirror is typically used to provide bias currents and active loads to circuits. Current mirrors may typically be constructed using various types of semiconductor switches such as a metal oxide semiconductor field effect transistor (MOSFET), field effect transistor (FET), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT) or Schottky transistor.

Reference is now made to FIG. 2 which shows a level shifter circuit 20 according to conventional art. Level shifter circuit 20 includes inverting amplifier A, resistors R1 and R2 (or equivalent loads), switches TCM1, TCM2, T1 and T2 which are preferably insulated gate field effect transistors (IGFETs). A current mirror circuit in level shifter circuit 20 is shown with the gate of IGFET TCM1 is connected to the gate (G) of a IGFET TCM2, along with both of the sources (S) of TCM1 and TCM2 typically connected to ground. A link connects the drain (D) of TCM1 to the gates (G) of TCM1 and TCM2. The drain (D) of TCM1 also connects to voltage supply (V_(cc)) via a resistor (not shown) to form current source I.

The drain of TCM2 connect to the sources (S) of IGFETS T1 and T2. The drain (D) of T1 connects to voltage supply (V_(cc)) through resistor R1. The drain (D) of T2 connects to voltage supply (V_(cc)) through resistor R2. The floating output voltage (Vf) of circuit 20 may be between voltage supply (V_(cc)) and node X or may be between voltage supply (V_(cc)) and node Y. Voltage input terminal (Control) is connected to the gate (C) of IGFET T2 and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T1 via inverting amplifier A.

In operation, shifter circuit 20 current I flows through resistors R1 or R2 which are referenced to floating output voltage (Vf) by virtue of current I flowing through resistors R1 or R2. The switching time for IGFETs T1 and T2 is typically a function of the miller drain capacitors of T1 and T2 plus all parasitic capacitances of T1 and T2 that are charged by the current I to a voltage swing value of the voltage input terminal (Control). IGFET T1 and resistor R1 are connected in circuit 20 as a common source (S) amplifier with output on node X common to the input from voltage input terminal Control. Similarly, IGFET T2 and resistor R2 are connected in circuit 20 as a common source (S) amplifier with output on node Y common to the inverse of input voltage input terminal Control. The bandwidth of the common-source amplifier typically tends to be low, due to high capacitance resulting from the Miller effect. The Miller effect accounts for the increase in the equivalent input capacitance of a common source (S) amplifier due to amplification of the capacitance between the input and output terminals. The additional input charge (Q_(CM)) due to the Miller effect for both IGFETs T1 or T2 is given by equation Eq. 2 below:

$\begin{matrix} {Q_{CM} = {\frac{dV}{dt}\left( {C_{GD} + C_{DS} + C_{p}} \right)}} & {{Eq}.\; 2} \end{matrix}$ C_(P)=Parasitic capacitance of the drain (D) of T1 or T2 C_(GD)=The capacitance between gate (C) and drain (D) of T1 or T2 C_(DS)=The capacitance between drain (D) and source (S) of T1 or T2 V=Voltage at node X for T1 or voltage at node Y for T2

Where even a small parasitic capacitance C_(GD) between gate (G) and drain (D) may become a large influence in the frequency response and hence bandwidth of the common source amplifier. A low bandwidth due to the effect of Miller capacitance typically reduces switching speed of the common source amplifier. Additionally, with a level shifter like shifter circuit 20, the switching times of IGFETs T1 and T2 are typically proportional to current consumption in resistors R1 and R2 because current in resistors R1 and R2 charges the Miller capacitance (C_(M)=C_(P)+C_(GD)+C_(DS)).

The terms “field-effect transistor (FET) switch” is used herein interchangeably and equivalently with the term “bipolar junction transistor (BJT) switch”. Whereby the gate of the FET switch is equivalent to the base of the BJT switch, the drain of the FET switch is equivalent to the collector of the BJT switch and the source of the FET switch is equivalent to the emitter of the BJT switch.

The term “leg of a switch” as used herein, refers to the actuation of a gate (of an FET) by application of a voltage to the gate for example, which causes a reduction in impedance between a drain and a source (of the FET). The reduction in impedance between the drain and the source (of the FET) is considered equivalent to the connection together of two contacts of a mechanical switch (e.g. single pole double throw switch (SPDT)).

The terms “charging” and “discharging” in the context of the present invention in reference to charging and discharging a capacitor, are used herein interchangeably except that current flow while charging and discharging is usually in the opposite direction.

The term “switch” as used herein refers to any of: silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, mechanically operated single pole double pole switch (SPDT), SPDT electrical relay, SPDT reed relay, SPDT solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), and triode for alternating current (TRIAC).

An ideal switch takes no time to go from off to on or from on to off. The switching time of the ideal switch is therefore zero. The term “switching time” as used herein refers to a finite period of time it takes for a switch to go from being in an “off” state to an “on” state or from the “on” state to the “off” state.

The terms “on” and “off” as used herein, when applied to a switch, refer to an increased current value flowing through the switch when the switch is “on” compared to the relative decreased current value flowing through the switch when the switch is “off”.

The term “minimal current” as used herein refers to the relative decreased current value flowing through a switch when the switch is off when compared to an increased current value flowing through the switch when the switch is on.

BRIEF SUMMARY

According to embodiments of the present invention there is provided a voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. The input voltage typically produces an output voltage on the output terminal based on the current. A charge storage circuit may be operatively attached to the input terminal and an input of the current mirror circuit. The charge storage circuit may include a capacitor or a battery.

The charge storage circuit has an inverting amplifier with an input connected to the input terminal. A capacitor connected between an output of the inverting amplifier and an anode of a diode. A cathode of the diode is connected to the input of the current mirror circuit. A second diode with a second cathode connected to the anode of the diode and a second anode connected to the electrical earth. A second inverting amplifier with a second input connected to the output of the inverting amplifier. A second capacitor connected between a second output of the second inverting amplifier and a third anode of a third diode. A third cathode of the third diode is connected to the input of the current mirror circuit. A fourth diode with a fourth cathode connected to the third anode of the third diode and a third anode connected to the electrical earth.

According to embodiments of the present invention there is provided a voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a switch driven by an input voltage applied to the input terminal to produce an output voltage on the output terminal based on a current drawn through the switch. The switch may be a silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, electrical relay, reed relay, solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), or triode for alternating current TRIAC. A current changing mechanism operatively connected to the switch. The current changing mechanism is preferably adapted for changing the current through the switch. The current changing mechanism is typically adapted to change the current when the switch is switched. The current changing mechanism is preferably adapted to provide a current control signal to a leg of the switch.

The level shifting circuit optionally includes further, a current mirror circuit having an output connected between the switch and an electrical earth. A charge storage circuit operatively attached to the input terminal and an input of the current mirror circuit and a second charge storage circuit operatively attached to the output terminal. The second charge storage circuit may include either a capacitor or a battery.

According to embodiments of the present invention there is provided a method to operate a voltage level shifting circuit. The level shifting circuit typically includes a switch which has an input terminal and an output terminal and a current mirror circuit having a current-mirror circuit output. The switch is connected in series with the current-mirror circuit output and an electrical earth, wherein a charge storage circuit is attached to the input terminal and an input of the current mirror circuit.

The method applies a voltage on the input terminal thereby driving a current through the switch and the current-mirror circuit output. The current is preferably a minimal value prior to the applying of the voltage. The charge storage circuit is typically charged prior to the applying of the voltage. The driving typically provides a voltage on the output terminal. The current is preferably increased by a discharge of the charge storage circuit into the input of the current mirror circuit. The current is preferably increased by switching the switch on. The current may also be increased at a time just prior to the switching the switch on. The current is preferably decreased by switching the switch off. The current may be further decreased by a charge of said charge storage circuit from said input of said current mirror circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 shows a current mirror circuit according to conventional art.

FIG. 2 shows a level shifter circuit according to conventional art.

FIG. 3a shows a general circuit diagram of a level shifter circuit, according to an embodiment of the present invention.

FIG. 3b shows a level shifter circuit, according to an embodiment of the present invention.

FIG. 4 shows a method to operate the level shifter circuit shown in FIG. 3b , according to an embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures.

Before explaining embodiments of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

By way of introduction, an embodiment of the present invention is directed to allow high current consumption only in the switching time. After the switching time, current is typically reduced to maintain low current consumption and allow for current overflow (by use of diodes) to the output floating voltage of the shifter circuit.

Reference is now made to FIG. 3a which shows a general circuit diagram of a level shifter circuit 30 a, according to an embodiment of the present invention. The drain (D) of T1 connects to voltage supply (V_(cc)) through resistor R1. The drain (D) of T2 connects to voltage supply (V_(cc)) through resistor R2. Capacitor CH1 is connected in parallel with resistor R1. Capacitor CH2 is connected in parallel with resistor R2. The anode of diode D6 is connected to the anode of diode D5. The connected anodes of D5 and D6 may provide one output terminal of floating output voltage Vf. The other terminal of floating output voltage Vf is connected to voltage power supply V_(cc). The cathode of diode D6 is connected to node X and the cathode of diode D5 is connected to node Y. Voltage input terminal (Control) is connected to the gate (G) of IGFET T1 and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T2 via inverting amplifier A1. The sources (S) of IGFET T1 and T2 are connected together and connect to one end of current controlled source 36. The other end of source 36 is connected to electrical earth. Flow of current through source 36 is controlled by current control line 38.

Reference is now made to FIG. 3b which shows a level shifter circuit 30 b, according to an embodiment of the present invention. Level shifter 30 b is a more detailed embodiment of level circuit 30 a shown in FIG. 3a . Shifter circuit 30 b additionally includes inverting amplifiers A1, A2 and A3, capacitors CH1 and CH2 and diodes D1, D2, D3, D4, D5 and D6. Switches TCM1, TCM2, T1 and T2 which are preferably insulated gate field effect transistors (IGFETs). A current mirror circuit in level shifter circuit 30 b is shown with the gate of IGFET TCM1 is connected to the gate (G) of a IGFET TCM2, along with both of the sources (S) of TCM1 and TCM2 typically connected to ground. A link connects the drain (D) of TCM1 to the gates (G) of TCM1 and TCM2. The drain (D) of TCM1 also connects to voltage supply (V_(cc)) via a resistor (not shown) to form current source I.

The drain of TCM2 connect to the sources (S) of IGFETS T1 and T2. The drain (D) of T1 connects to voltage supply (V_(cc)) through resistor R1. The drain (D) of T2 connects to voltage supply (V_(cc)) through resistor R2. Capacitor CH1 is connected in parallel with resistor R1. Capacitor CH2 is connected in parallel with resistor R2. The anode of diode D6 is connected to the anode of diode D5. The connected anodes of D5 and D6 may provide one output terminal of floating output voltage Vf. The other terminal of floating output voltage Vf is connected to voltage power supply V_(cc). The cathode of diode D6 is connected to node X and the cathode of diode D5 is connected to node Y. Voltage input terminal (Control) is connected to the gate (G) of IGFET T1 and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T2 via inverting amplifier A1. Voltage input terminal (Control) is also connected to the input of inverting amplifier A2. The output of inverting amplifier A2 is connected to the input of inverting amplifier A3. The output of inverting amplifier A2 is also connected to one end of capacitor Ci1, the other end of capacitor Ci1 connects to the anode of diode D1 and the cathode of diode D2. The cathode of diode D1 connects to the gates (C) of switches TCM1 and TCM2. The anode of diode D2 connects to ground. The output of inverting amplifier A3 is connected to one end of capacitor Ci2, the other end of capacitor Ci2 connects to the anode of diode D4 and the cathode of diode D3. The cathode of diode D4 connects to the gates (G) of switches TCM1 and TCM2. The anode of diode D3 connects to ground. Switch TCM2 is the realization of current controlled source 36 shown in FIG. 3a along with current control line 38 provided by the connection to the gate (G) of switch TCM2.

Reference is now made to FIG. 4 which shows a method 401 to operate level shifter circuit 30 b shown in FIG. 3, according to an embodiment of the present invention. The explanation of method 401 that follows, relies for the most part on the circuit symmetry of level shifter circuit 30 b operating in a dynamic mode of operation and as such reference will be made to one half of circuit 30 b, namely the operation of switch T1 and associated components. Accordingly as such, the operation of switch T1 during the dynamic mode of operation of circuit 30 b typically corresponds to the opposite operation of switch T2 and associated components. That is to say, by virtue of inverting amplifier A1, when switch T1 is switched on, switch T2 is switched off and vice versa. Similarly, by virtue of amplifiers A2 and A3 the charging of capacitor Ci1 via diodes D1 and D2 corresponds to the opposite charging of capacitor Ci2 via diodes D4 and D3 respectively and vice versa. Additionally by virtue switch T1 being on and switch T2 off and vice versa, the charging of capacitor CH1 and diode D6 corresponds to the opposite charging of capacitor CH2 and diode D5 respectively.

During quiescent operation of circuit 30 b when no voltage is applied to voltage input terminal (Control), capacitors Ci1 and Ci2 are charged (step 403). Current I is at a minimal value and both switches T1 and T2 are off.

During the dynamic mode of operation, voltage input terminal (Control) has a voltage level applied (step 405) such that switch T1 is turned on and transistor T2 is turned off. The current I is pushed high by the discharge of capacitor Ci1 and consequently the current through switch T1, which mirrors current I, is increased (step 407). The change in current I, causes the output voltage Vf to vary in sympathy with the input voltage effectively causing a voltage level shift of the input voltage applied to voltage input terminal (Control) in step 405. The increased current through switch T1 quickly charges floating capacitor CH1 and Miller capacitance of switch T1, which reduces the switching time of switch T1. Overflow of the charging of capacitor CH1 is typically discharged by diode D6.

Shifter circuit 30 b can either use or not use capacitors CH1 and CH2. The reason for capacitors CH1 and CH2 is to prevent a mismatch of the level shifter circuit 30 b output via switches T1 and T2 not being matched.

The definite articles “a”, “an” is used herein, such as “a charge storage circuit”, “a switch” have the meaning of “one or more” that is “one or more charge storage circuits” or “one or more switches”.

Although selected embodiments of the present invention have been shown and described, it is to be understood the present invention is not limited to the described embodiments. Instead, it is to be appreciated that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and the equivalents thereof. 

The invention claimed is:
 1. A circuit comprising: a first circuit portion comprising a first switch and a resistor and configured to produce, responsive to an input voltage to a control input of the first switch, an output voltage by passing current through the resistor and the first switch; a second circuit portion comprising a second switch and configured to draw, responsive to a control input of the second switch, the current through the first switch and the resistor; and a third circuit portion comprising a charge storage device and configured to discharge into the control input of the second switch, responsive to the input voltage, a charge stored in the charge storage device, wherein the third circuit portion is configured to control the second circuit portion to decrease, in response to the input voltage being unchanged, the current through the first switch and the resistor.
 2. The circuit of claim 1, wherein the third circuit portion is configured to control the second circuit portion to increase, in response to a change in the input voltage, the current through the first switch and the resistor.
 3. The circuit of claim 1, wherein the first circuit portion comprises a level shifting circuit.
 4. The circuit of claim 1, wherein the second circuit portion comprises a current mirror circuit.
 5. The circuit of claim 1, wherein the charge storage device is connected to the input voltage via an inverting amplifier, and wherein the control input of the first switch is configured to receive the input voltage without inversion.
 6. The circuit of claim 1, wherein each of the first switch and the second switch is selected from a group consisting of: a silicon controlled rectifier (SCR), an insulated gate bipolar junction transistor (IGBT), a bipolar junction transistor (BJT), a field effect transistor (FET), a junction field effect transistor (JFET), a switching diode, an electrical relay, a reed relay, a solid state relay, an insulated gate field effect transistor (IGFET), a diode for alternating current (DIAC), and a triode for alternating current TRIAC.
 7. The circuit of claim 1, wherein the first circuit portion is connected between a voltage source and the second circuit portion, and wherein the second circuit portion is connected between the first circuit portion and ground.
 8. A circuit comprising: a first switch having a control input connected to a first node, wherein the first switch is further connected between a second node and a third node; a current-controlled source connected to the third node and comprising a control input connected to a fourth node; and a charge storage circuit connected between the first node and comprising a control input connected to the fourth node, wherein the charge storage circuit is configured to control the current-controlled source to increase, in response to a change in voltage at the first node, a current through the first switch between the second node and the third node, wherein the charge storage circuit is further configured to control the current-controlled source to increase the current by discharging a stored charge into the fourth node.
 9. The circuit of claim 8, wherein the charge storage circuit is further configured to control the current-controlled source to decrease, in response to the voltage at the first node being unchanged, the current through the first switch between the second node and the third node.
 10. The circuit of claim 8, wherein the charge storage circuit comprises a first capacitor and a second capacitor, the circuit further comprising: a first inverting amplifier comprising an input connected to the first node and comprising an output connected to the first capacitor; and a second inverting amplifier comprising an input connected to the output of the first inverting amplifier and comprising an output connected to the second capacitor.
 11. The circuit of claim 8, further comprising an inverting amplifier and a second switch, wherein the control input of the first switch is directly connected to the first node and a control input of the second switch is connected to the first node via the inverting amplifier, wherein the second switch is further connected between a fifth node and the third node.
 12. The circuit of claim 8, wherein the first switch is selected from a group consisting of: a silicon controlled rectifier (SCR), an insulated gate bipolar junction transistor (IGBT), a bipolar junction transistor (BJT), a field effect transistor (FET), a junction field effect transistor (JFET), a switching diode, an electrical relay, a reed relay, a solid state relay, an insulated gate field effect transistor (IGFET), a diode for alternating current (DIAC), and a triode for alternating current TRIAC.
 13. The circuit of claim 8, wherein the second node is connected between a voltage source and the first switch, and wherein the current-controlled source is connected between the third node and ground.
 14. The circuit of claim 8, further comprising a first voltage output node connected to the second node via a diode and a second voltage output node connected to the second node via a resistor.
 15. A circuit comprising: a first circuit portion comprising a first switch and a resistor and configured to produce, responsive to an input voltage to a control input of the first switch, an output voltage by passing current through the resistor and the first switch; a current mirror comprising a second switch and configured to draw, responsive to a control input of the second switch, the current through the first switch and the resistor; and a second circuit portion comprising a charge storage device and configured to discharge into the control input of the second switch, responsive to the input voltage, a charge stored in the charge storage device.
 16. The circuit of claim 15, wherein the second circuit portion is configured to control the current mirror to increase, in response to a change in the input voltage, the current through the first switch and the resistor.
 17. The circuit of claim 15, wherein the second circuit portion is configured to control the current mirror to decrease, in response to the input voltage being unchanged, the current through the first switch and the resistor.
 18. The circuit of claim 15, wherein the first circuit portion comprises a level shifting circuit.
 19. The circuit of claim 15, wherein the charge storage device is connected to the input voltage via an inverting amplifier, and wherein the control input of the first switch is configured to receive the input voltage without inversion.
 20. The circuit of claim 15, wherein the first circuit portion is connected between a voltage source and the current mirror, and wherein the current mirror is connected between the first circuit portion and ground. 